The present invention relates in general to logic analyzer probes and in particular to a probe which may be retargeted to access the pins of a variety of different microprocessors.
Logic analyzers typically monitor the address and data busses and the control lines appearing on the pins of a microprocessor chip and display on a screen the sequential history of the microprocessor operation, including the states of the control lines and of the address and data busses of the processor. Logic analyzers often access the address, data and control lines of the processor by means of a probe inserted between the microprocessor and its socket in the system under test. Such a probe typically comprises a replacement plug having a set of pins matching the microprocessor pin arrangement, for inserting into a motherboard in place of the microprocessor, and a socket into which the microprocessor can be inserted. Internal probe wiring connects the pins of the microprocessor to the appropriate replacement plug pins and to buffers within the probe which can transmit the data appearing at the pins of the microprocessor to the logic analyzer data acquisition circuits.
The data acquisition circuits of a logic analyzer typically store the acquired data characterizing each microprocessor transaction in a random access acquisition memory, with data representing successive transactions being stored sequentially at successive addresses. Since the states of data and address busses of a microprocessor are only valid for a portion of a transaction cycle, a transaction analyzer is normally provided to monitor selected control lines of a microprocessor, to determine when a valid transaction has occurred and to generate a write strobe signal to the acquisition memory. The acquisition memory then stores the acquired data.
In the prior art, much of the data acquisition portion of a logic analyzer, including the probe, was specifically designed for use with only one type of microprocessor because different microprocessors have different pin arrangements, different types of control lines, different types of transactions and different timing requirements. Therefore a separate probe, transaction analyzer, and related data acquisition circuit components must be designed and constructed to be specifically targeted for each type of microprocessor to be tested. This places a heavy cost burden on users performing logic analysis on a variety of different microprocessors. What is needed and would be useful would be a probe which could be used in conjunction with a logic analyzer having a programmable transaction analyzer, and which could be retargeted to acquire data from a number of different types of microprocessors with a minimum change in probe hardware and with no change in logic analyzer data acquisition hardware.